1. Field of the Invention
This invention relates generally to programmable logic devices and more particularly to a programmable pattern generator adapted for testing memory devices.
2. Description of the Related Art
Testing systems have been developed for determining the proper functioning of semiconductor devices, such as memory devices. The testing system typically writes a number of data patterns simultaneously to a group of memory devices under test. Memory devices often have multiple banks of memory which may be grouped into blocks and sub-blocks. The internal organization of the memory device is such that sequential addresses do not necessarily indicate adjacent locations. Also, due to the manner in which cells in a memory device are typically designed, a logic “1” on an external data line may actually be stored as a logic “0” in a given cell.
The particular internal organization of the memory device as related to the location of sequential address is referred to as its address topology, and the organization of the memory device with respect to the way data is stored is referred to as its data topology. Different memory device models typically have different address and data topologies, depending on their specific layout, size, etc.
To ensure that a test is performed as intended, the testing system must account for both the address topology and the data topology while performing the test. Various data patterns used for testing a memory device are well known in the art. For example, a checkerboard data pattern involves writing alternating logic “1” and logic “0” values in a block of cells. To ensure that the block of cells is contiguous, the testing system considers the address topology when deciding the particular cells to access. Also, the testing system considers the data topology when determining whether to write a logic “1” or a logic “0” to a particular cell to achieve the desired checkerboard pattern. Address and data topologies are typically defined by logic functions having exclusive OR, AND, and/or OR components. The logic functions are performed on the row and/or column address to account for the particular topologies.
Generally, program loops are used to implement the testing patterns used to perform a particular test. Typically, a number of instructions are used to control the looping. For example, a comparison is conducted to determine if a loop terminating condition is met at the end of the loop. If the loop terminating condition is not met the program is instructed to branch back to the starting point, and if the loop terminating condition is met, the program branches to the next instruction. This plurality of steps to control a loop adds overhead clock cycles (i.e., no testing of the device is being performed during these instructions). The number of overhead clock cycles is significant due to the number of loops typically used to complete a testing pattern. Due to the overhead, the time required to complete a test pattern using a program loop is increased.
Prior testing systems have typically used cross bar switches to manipulate a particular row or column address received from an address generator and access lookup tables based on the manipulated address. A cross bar switch typically has the same number of inputs and outputs and allows any of the inputs to be routed to any of the outputs. For example, the third input may be routed to the tenth output. In effect, a cross bar switch allows an address to be rearranged in a predetermined fashion. A cross bar switch performs no logic operations, however, the lookup tables are programmed based on the address and data topologies of the memory device to provide outputs based on logical combinations of the inputs.
Cross bar switches typically consume large amounts of circuit area and are not easily integrated with other components of the testing system, resulting in more complicated and costly circuits.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.